The present disclosure generally relates to electrical circuits, and more specifically, to circuits for a successive approximation register (SAR) analog-to-digital converter (ADC) and methods of temperature compensation in a SAR ADC.
A successive approximation register (SAR) analog-to-digital converter (ADC) commonly employs a capacitive digital-to analog converter (CDAC) in which the constituent capacitors are switched between a reference voltage and ground to set an appropriate output voltage. Although an ideal CDAC produces an analog output voltage or current that is precisely linear, real-world CDACs are subject to influence by external factors, such as temperature, and are therefore susceptible to errors. For example, as temperature varies, the CDAC reference voltage may drift and, accordingly, a gain error may be introduced. While an SAR ADC can be calibrated to compensate for gain errors at a constant temperature, it is much more difficult to compensate for gain errors resulting from temperature variations; i.e., it is impractical for circuit designers to calibrate to compensate for gain errors resulting from temperature drift of voltage output by the CDAC.
Accordingly, improved circuits and methods for controlling the gain of an SAR ADC to compensate for variations in temperature are needed.